In multiplane or multilevel wiring technology, a number of relatively thin substrates are used to support conductor patterns and are assembled into a laminar stack with connections that have come to be known in the art as vias extending through the laminations and interconnecting the wiring on the individual laminations. The technology is usually practiced using patterned conductor deposition techniques that after assembly in a stack the patterns are interconnected through hole patterns aligned between some or all laminations into a unitary wiring package. In the semiconductor technology, the semiconductor chips are usually positioned on the upper surface of the stacked wiring package.
As the overall performance specifications have increased, the wiring structures have been assembled with the high frequency impedance parameters becoming a more prominent consideration.
In the Microelectronics Packaging Handbook edited by R. R. Tummala and E. J. Rymaszewski, Van Nostrand, 1985, pages 18, 138 and 154, there is recognition of the impedance problem.
As the number of laminations still further increased, and the current carrying requirements of power conductors as contrasted with signal conductors became greater, techniques appeared in the art in U.S. Pat. Nos. 4,649,417 and 4,827,327 that distinguished in the wiring structure between signal and power conductors. A limiting aspect of such an approach to the problem is that a very early decision must be made as to where which type is to be located which reduces flexibility in assembling the wiring configuration.
Heretofore in the art, the impedance problem could be contained. Reference metallization was used to control the impedance of the conductors on the lamination surfaces and the few mils of lamination thickness did not produce significant signal delays where the vias passed through the dielectric.
The performance required in the art has now reached the point where delays in signal transmission in the picosecond range, as is encountered in a mismatched impedance via passing through a few plane pairs of dielectric laminations, can no longer be tolerated.